In a solid-state imaging device such as an image sensor, a peripheral logic region serving as, for example, a horizontal shift register or the like is disposed around an image pickup region (a pixel region) (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2003-60192). Here, a step of forming a diffusion layer for inter-pixel separation within the pixel region (pixel array) and a step of forming a deep diffusion layer for electrical connection to a substrate within the peripheral logic region are largely different in a manufacturing step thereof. Therefore, it is difficult to apply a common step to the step of forming a diffusion layer for such a inter-pixel separation and the step of forming the deep diffusion layer. This is because of special factors such as using photoresist with high aspect as a mask in the forming step of the diffusion layer for the pixel separation in the pixel region, necessity for formation at the deepest position of a semiconductor substrate, and the like.
Here, a high energy ion implantation step applied when ions are implanted at the deepest position of the semiconductor substrate is an expensive step requiring a very high manufacturing cost. Therefore, it is desired to eliminate such a high energy ion implantation step in view of reduction of manufacturing cost.
In the conventional configuration and a manufacturing method thereof, however, since the number of times of the high energy ion implantation step performed when ions are implanted at a deep position of the semiconductor substrate cannot be eliminated, there is such a tendency that the conventional configuration and manufacturing method are disadvantageous regarding the reduction of manufacturing cost.
As one example, when it is tried to form the deep diffusion layer, for example, at a depth position of about 2.0 μm from a silicon (Si) substrate surface, high acceleration energy of about 1600 keV (1.6 MeV) is required therefor.
Further, for example, when it is tried to form the diffusion layer for the pixel separation at a depth position of about 2.7 μm from the silicon (Si) substrate surface like the above, high acceleration energy of 2000 keV (2.0 MeV) is required therefor.
Thus, in the conventional configuration and a manufacturing method thereof, since the high energy ion implantation step must be performed at least two times and the number of times of the high energy ion implantation step cannot be reduced, there is such a tendency that the conventional configuration and manufacturing method are disadvantageous regarding the reduction of manufacturing cost.